CPHA=CAPTURED, LSBF=MSB_FIRST, BYSW=DISABLED, CONTC=START, CPOL=INACTIVE_LOW, RXMSK=NORMAL, WIDTH=ONEBIT, PRESCALE=DIVIDEBY1, PCS=TX_PCS0, CONT=DISABLED, TXMSK=NORMAL
Transmit Command Register
| FRAMESZ | Frame Size |
| WIDTH | Transfer Width 0 (ONEBIT): 1 bit transfer 1 (TWOBIT): 2 bit transfer 2 (FOURBIT): 4 bit transfer |
| TXMSK | Transmit Data Mask 0 (NORMAL): Normal transfer 1 (MASK): Mask transmit data |
| RXMSK | Receive Data Mask 0 (NORMAL): Normal transfer 1 (MASK): Receive data is masked |
| CONTC | Continuing Command 0 (START): Command word for start of new transfer 1 (CONTINUE): Command word for continuing transfer |
| CONT | Continuous Transfer 0 (DISABLED): Continuous transfer is disabled 1 (ENABLED): Continuous transfer is enabled |
| BYSW | Byte Swap 0 (DISABLED): Byte swap is disabled 1 (ENABLED): Byte swap is enabled |
| LSBF | LSB First 0 (MSB_FIRST): Data is transferred MSB first 1 (LSB_FIRST): Data is transferred LSB first |
| PCS | Peripheral Chip Select 0 (TX_PCS0): Transfer using LPSPI_PCS[0] 1 (TX_PCS1): Transfer using LPSPI_PCS[1] 2 (TX_PCS2): Transfer using LPSPI_PCS[2] 3 (TX_PCS3): Transfer using LPSPI_PCS[3] |
| PRESCALE | Prescaler Value 0 (DIVIDEBY1): Divide by 1 1 (DIVIDEBY2): Divide by 2 2 (DIVIDEBY4): Divide by 4 3 (DIVIDEBY8): Divide by 8 4 (DIVIDEBY16): Divide by 16 5 (DIVIDEBY32): Divide by 32 6 (DIVIDEBY64): Divide by 64 7 (DIVIDEBY128): Divide by 128 |
| CPHA | Clock Phase 0 (CAPTURED): Data is captured on the leading edge of SCK and changed on the following edge of SCK 1 (CHANGED): Data is changed on the leading edge of SCK and captured on the following edge of SCK |
| CPOL | Clock Polarity 0 (INACTIVE_LOW): The inactive state value of SCK is low 1 (INACTIVE_HIGH): The inactive state value of SCK is high |